Pratik Mhasawade
Digital IC Design & Verification | Embedded AI | IoT | Drone Tech
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I am an Electronics & Telecommunication Engineering undergraduate passionate about Edge AI acceleration, Digital IC Design & Verification, RTL Development, and RISC-V microarchitecture and Embedded Systems. I have hands-on experience in Verilog/SystemVerilog, FPGA prototyping, and functional verification, including designing a 32-bit RISC-V processor on an FPGA and developing pipelined hardware accelerators. I am seeking internship opportunities in Digital IC Design, RTL Design, and Verification Engineering to apply my skills in real-world semiconductor systems.
~Pratik Mhasawade
Education
Education
B.Tech – Electronics & Telecommunication Engineering (CGPA: 8.84/10 | Aug 2023 – Jun 2027)
Vidya Pratishthan’s Kamalnayan Bajaj Institute of Engineering & Technology, Baramati.
Honors in VLSI (CGPA: 8.68/10 | July 2024 – Nov 2026)
Vidya Pratishthan’s Kamalnayan Bajaj Institute of Engineering & Technology, Baramati.
Tehnical Skills
Tehnical Skills
Programming: Verilog, SystemVerilog, C, Python, Perl.
RTL & Microarchitecture: Datapath Design, Control FSM, Register File, ALU, Pipelining, Memory-Mapped I/O, Timing-Aware RTL
Architecture: RISC-V (RV32IMAC), Wishbone, Basic AMBA
Verification: Directed Testing, UVM-based Constrained Random Verification, TLM, Functional Coverage
Platforms / FPGA: Xilinx Vivado (Synthesis, Implementation, Timing Analysis), Artix-7 (35T/100T) , NVIDIA Jetson Nano .
HLS: Scheduling, Allocation & Binding, Datapath/Controller Synthesis (Vitis HLS)
Embedded & Edge AI: Embedded Systems, Edge AI Deployment, HW–SW Co-Design, TensorRT, YOLO .
Protocols / Interfaces: AMBA(AXI), UART, SPI, I2C, etc.
Tools: Git, Linux
Projects
Projects
• Designed parameterized 4×4 matrix multiplication IP with 3-stage pipelined datapath and balanced adder-tree architecture.
• Implemented valid-signal alignment, clock-enable control, and timing-aware RTL structure on Artix-7 FPGA.
• Verified using constrained-random testbench; achieved 95% functional coverage, 3-cycle deterministic latency, and 1-result-per-cycle throughput.
• Designed RV32I processor with 5-stage pipeline (IF–ID–EX–MEM–WB) and modular datapath/control architecture.
• Implemented hazard detection (load-use stalls) and data forwarding unit to resolve RAW hazards and maintain pipeline efficiency.
• Deployed YOLOv8-based crowd density detection model on NVIDIA Jetson Nano (4GB), achieving real-time inference ( 30–34 FPS).
• Optimized model using TensorRT and FP16 precision for reduced latency and improved throughput.
• Designed a fully edge-based processing pipeline, eliminating cloud dependency.
Achievements
Achievements
• Winner, National Level Smart India Hackathon 2025 – Student Innovation (Hardware Edition) (Team Leader)
• Grand Finale Qualifier (Top 100), MeitY Chip2Startup Grand Challenge – RISC-V Drone Flight Controller Architecture (Team Leader)
• Awardee, Cummins India Nurturing Brilliance Scholarship, 2025
• Consolation Prize Winner – IET K K Wagh Expo 2026 (25,000 Award)
• Won 1st Prize at KUMBHA Hackathon 2K25 organized by the IEEE Local Chapter, VPKBIET, Baramati.
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